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layout versus schematic中文是什么意思

  • 布局与原理图比较
  • 配置、检图对照

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  • 例句与用法
  • At last , the layout is verified with cadence verification tools , dracula . drc ( design rule cherker ) and lvs ( layout versus schematic ) have been done successfully , which improve the feasibility of the layout design . so the whole ic design flow , from the front end to the back end of a circuit design , is completed
    接着应用无锡上华标准0 . 6umcmos工艺提供的元器件模型参数进行了电路仿真,并根据尺寸设计规则设计了整体电路的的版图,最后运用cadence中的版图验证工具集dracula对电路版图成功地进行了drc ( designrulecherker ) 、 lvs ( layoutversusschematic )验证,证明了电路版图设计的可行性,完成了ic设计从前端到后端的设计流程。
  • 百科解释
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.
详细百科解释
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Last modified time:Tue, 19 Aug 2025 00:29:56 GMT

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